GATE-DRIVE-ON-ARRAY CIRCUIT FOR USE WITH OXIDE SEMICONDUCTOR THIN-FILM TRANSISTORS

摘要

A gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (VSS1, VSS2) that are reduced step by step and low potentials of a high-frequency clock signal (CK(n)) and a low-frequency clock signal (LC1, LC2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (CK(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (Q(N)) and the output terminal (G(N)) so as to ensure the first node (Q(N)) and the output terminal (G(N)) can supply the outputs normally without generating signal distortion.

主权项

1. A gate-drive-on-array (GOA) circuit for use with oxide semiconductor thin-film transistors, comprising multiple stages of cascaded GOA units, wherein, with N being a positive integer, the Nth-stage GOA unit comprises an up-pull control portion, an up-pull portion, a down-transfer portion, a first down-pull portion, a bootstrap capacitor portion, and a down-pull holding circuit portion;
the up-pull control portion comprising an eleventh transistor, where the eleventh transistor has a gate terminal electrically connected with a drive signal terminal of a second-anterior-stage GOA unit of the Nth-stage GOA unit, the (N−2)th-stage GOA unit, a source terminal electrically connected with an output terminal of the second-anterior-stage GOA unit of the Nth-stage GOA unit, the (N−2)th-stage GOA unit, and a drain terminal electrically connected with a first node; the up-pull portion comprising a twenty-first transistor, where the twenty-first transistor has a gate terminal electrically connected with the first node, a source terminal electrically connected with a high-frequency clock signal, and a drain terminal electrically connected with an output terminal; the down-transfer portion comprising a twenty-second transistor, where the twenty-second transistor has a gate terminal electrically connected with the first node, a source terminal electrically connected with the high-frequency clock signal, and a drain terminal electrically connected with a drive output terminal; the first down-pull portion comprising a forty-first transistor, where the forty-first transistor has a gate terminal electrically connected with an output terminal of a third-posterior-stage GOA unit of the Nth-stage GOA unit, the (N+3)th-stage GOA unit, a drain terminal electrically connected with the first node, and a source terminal electrically connected with the output terminal; the bootstrap capacitor portion comprising a capacitor, where the capacitor has an end electrically connected with the first node and an opposite end electrically connected with the output terminal; the down-pull holding portion comprising: a forty-second transistor, where the forty-second transistor has a gate terminal electrically connected with a second node, a source terminal electrically connected with the first node, and a drain terminal electrically connected with a second constant-voltage negative potential source; a thirty-second transistor, where the thirty-second transistor has a gate terminal electrically connected with the second node, a source terminal electrically connected with the output terminal, and a drain terminal electrically connected with a first constant-voltage negative potential source; a fifty-first transistor, where the fifty-first transistor has a gate terminal and a source terminal both of which are electrically connected with a first low-frequency signal source and a drain terminal electrically connected with a fourth node; a fifty-second transistor, where the fifty-second transistor has a gate terminal electrically connected with the first node, a source terminal electrically connected with the fourth node, and a drain terminal electrically connected with the first constant-voltage negative potential source; a fifty-third transistor, where the fifty-third transistor has a gate terminal electrically connected with the fourth node, a source terminal electrically connected with the first low-frequency signal source, and a drain terminal electrically connected with the second node; a fifty-fourth transistor, where the fifty-fourth transistor has a gate terminal electrically connected with a second low-frequency signal source, a source terminal electrically connected with the first low-frequency signal source, and a drain terminal electrically connected with the second node; a fifty-fifth transistor, where the fifty-fifth transistor has a gate terminal electrically connected with the first node, a source terminal electrically connected with the second node, and a drain terminal electrically connected with a third node; a sixty-fourth transistor, where the sixty-fourth transistor has a gate terminal electrically connected with the first low-frequency signal source, a source terminal electrically connected with the second low-frequency signal source, and a drain terminal electrically connected with the third node; a sixty-third transistor, where the sixty-third transistor has a gate terminal electrically connected with a fifth node, a source terminal electrically connected with the second low-frequency signal source, and a drain terminal electrically connected with the third node; a sixty-second transistor, where the sixty-second transistor has a gate terminal electrically connected with the first node, a source terminal electrically connected with the fifth node, and a drain terminal electrically connected with the first constant-voltage negative potential source; a sixty-first transistor, where the sixty-first transistor has a gate terminal and a source terminal both of which are electrically connected with the second low-frequency signal source and a drain terminal electrically connected with the fifth node; a thirty-third transistor, where the thirty-third transistor has a gate terminal electrically connected with the third node, a source terminal electrically connected with the output terminal, and a drain terminal electrically connected with the first constant-voltage negative potential source; and a forty-third transistor, where the forty-third transistor has a gate terminal electrically connected with the third node, a source terminal electrically connected with the first node, and a drain terminal electrically connected with the second constant-voltage negative potential source; and the first constant-voltage negative potential source being higher than the second constant-voltage negative potential source.