Systems and methods to mitigate program gate disturb in split-gate flash cell arrays

摘要

A memory circuit has control gate circuitry (104) and select gate circuitry (106). A first memory cell (122/124) has a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a first bit line for reading a logic state of the of the first memory cell, and a source. A second memory cell (150/152 or 158/160) having a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a second bit line for reading a logic state of the of the second memory cell, and a source. A source control circuit (102) that, during programming of the first memory cell, outputs a first voltage to the source of the first memory cell and keeps the source of the second memory cell floating.

主权项

1. A memory circuit, comprising:
control gate circuitry; select gate circuitry; a first memory cell having a control terminal of a control gate coupled to the control gate circuitry, a control terminal of a select gate coupled to the select gate circuitry, a drain of the select gate that is coupled to a first bit line for reading a logic state of the of the first memory cell, and a source of the control gate; a second memory cell having a control terminal of a control gate coupled to the control gate circuitry, a control terminal of a select gate coupled to the select gate circuitry, a drain of the select gate that is coupled to a second bit line for reading a logic state of the of the second memory cell, and a source of the control gate; and a source control circuit that, during programming of the first memory cell, outputs a first voltage to the source of the control gate of the first memory cell and keeps the source of the control gate of the second memory cell floating.