Controlling adjustable resistance bit lines connected to word line combs

摘要

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

主权项

1. A non-volatile memory, comprising:
a first word line comb structure, the first word line comb structure includes a first word line segment and a second word line segment connected to the first word line segment; a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes a first adjustable resistance local bit line and a first select gate, a first memory cell is arranged between the first adjustable resistance local bit line and the first word line segment, the first adjustable resistance local bit line is arranged between the first select gate and the first memory cell; and a second adjustable resistance bit line structure, the second adjustable resistance bit line structure includes a second adjustable resistance local bit line and a second select gate, a second memory cell is arranged between the second adjustable resistance local bit line and the second word line segment, the second adjustable resistance local bit line is arranged between the second select gate and the second memory cell, the first adjustable resistance local bit line is set into a conducting state during a memory operation, the second adjustable resistance local bit line is set into a non-conducting state during the memory operation.