Tunneling field effect transistor having a three-side source and fabrication method thereof

摘要

The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled. By forming the channel region using an epitaxy method subsequent to etching, it facilitates to form a steeper doping concentration gradient for the source region or form a hetero-junction. Moreover, the fabrication flow of the post-gate process facilitates to integrate a high-k gate dielectric/a metal gate having good quality, further improving the performance of the transistor.

主权项

1. A tunneling field effect transistor, comprising a semiconductor substrate (1), a channel region (6), a highly-doped source region (3), a lightly-doped drain region (4), a gate dielectric layer (7), and a control gate (8),
wherein the channel region (6) is in a cuboid shape; when viewing from a horizontal direction, a side of the channel region (6) extends into the highly-doped source region (3), and the other side thereof is connected to the lightly-doped drain region (4); when viewing from a vertical direction, the channel region (6) is located under the control gate (8) and the gate dielectric layer (7); the channel region (6) extending into the highly-doped source region (3) is surrounded at three sides by the highly-doped source region (3), while the channel region (6) not extending into the highly-doped source region (3) is surrounded by the semiconductor substrate (1); the control gate (8) is spaced apart from the lightly-doped drain region (4) by a horizontal interval; the control gate (8) covers the highly-doped source region (3) and a part of the channel region (6); the lightly-doped drain region (4) and the highly-doped source region (3) are doped with different types of impurities; the lightly-doped drain region (4) has a doping concentration between 5×1017 cm−3 and 1×1019 cm−3, and the highly-doped source region (3) has a doping concentration between 1×1019 cm−3 and 1×1021 cm−3.