| 摘要 |
<p>PURPOSE:To prepare verification data accurately and simply and to enable automatic verification of a device to be verified, by representing design specification of the device by a finite state machine model. CONSTITUTION:In the case of verification of a control board 29 of a refrigerator, for instance, first a virtual state and an internal time in an apparatus for verification are initialized. In a signal input element 13, next, an event and an action are extracted 15 and 17 respectively from data inputted from the control board 29. Then, it is verified whether or not they are a combination of an event and an action which can be generated in the current state. In the case when the event and the action which can not be generated exist, judgement is made as abnormality of verification and the process is ended. When a combination of those which can be generated is detected as the result of verification, the internal time is replaced by the time when the event and the action are generated, the virtual state is put in transition to a next state and thereby an internal state and the internal time are updated. Extractions are repeated until the data inputted to the signal input element 13 are up or until a forced end instruction is supplied from the outside.</p> |
