发明名称 OPTIMAL CIRCUIT DESIGN LAYOUT FOR HIGH PERFORMANCE BALL GRID ARRAY PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a trace layout and a tracing method for connecting the bonding pad of a semiconductor chip onto a printed wiring board. SOLUTION: A plurality of via holes 11 in rows and columns penetrate from the upper surface of a substrate 1 through the bottom surface, on which solder balls are provided fastened to each via hole. A plurality of pairs of traces 9 are provided on the upper surface. A via hole of an are trace 9 is extended to the other via hole of the trace 9 and is then extended to a plurality of via holes 11 in rows and columns. Traces of each pair have just one ball pitch space in between. Matching of the lengths are maximized, and parallelism and interval are maximized. Each trace of the pair is preferably maximized with respect to the geometrical array of the cross section. A pair of differential signals is applied to at least one of the trace pairs. Furthermore, this layout has another surface, that is between the upper surface and bottom surface and insulated from the upper surface and the bottom surface. A plurality of traces are disposed on this surface.
申请公布号 JPH11317471(A) 申请公布日期 1999.11.16
申请号 JP19990041955 申请日期 1999.02.19
申请人 TEXAS INSTR INC <TI> 发明人 STEARNS WILLIAM P;NOZAR HASSANZADEE
分类号 H05K1/02;H01L23/12;H01L23/498;H05K3/00 主分类号 H05K1/02
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