| 摘要 |
PROBLEM TO BE SOLVED: To attain the stable operation of a DLL circuit or the like even when the DLL circuits in the hierarchical structures of different accuracy are combined and power source jitter is generated by power source noise or external clock signal jitter, in a semiconductor device provided with a function for adjusting the phase of an external clock signal and generating an internal clock signal delayed just for a prescribed phase. SOLUTION: This device is provided with a first clock phase control circuit 1 for coarsely controlling the phase of the external clock signal and a second clock phase control circuit 2 for controlling the phase of the internal clock signal with the accuracy higher than that of the first clock phase control circuit 1, the phases are independently compared by the first and second clock phase control circuits 1 and 2 and when letting the phase control of the second clock phase control circuit 2 follow the operation of the first clock phase control circuit 1, the delay amount of respective plural delay elements in the first clock phase control circuit 1 is set larger than the power source jitter generated by the power supply noise or external clock signal jitter. |
