发明名称 Error Detection and Correction Circuit and Semiconductor Memory
摘要 Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.
申请公布号 US2008320368(A1) 申请公布日期 2008.12.25
申请号 US20080279177 申请日期 2008.08.12
申请人 HITACHI ULSI SYSTEMS CO., LTD. 发明人 IZUMITA MORISHI;TAKAYANAGI HIROSHI
分类号 G11C29/04;G06F11/07 主分类号 G11C29/04
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