发明名称 METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING HARD MASK PATTERNING
摘要 Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.
申请公布号 US2016247730(A1) 申请公布日期 2016.08.25
申请号 US201615050784 申请日期 2016.02.23
申请人 YOU Junggun;Choi Jeongmin;Kim Ingyum 发明人 YOU Junggun;Choi Jeongmin;Kim Ingyum
分类号 H01L21/8238;H01L29/78;H01L29/66 主分类号 H01L21/8238
代理机构 代理人
主权项 1. A method of fabricating a semiconductor device, comprising: forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, ones of the plurality of fin active regions extending parallel to each other in a first direction, wherein the plurality of fin active regions comprise a first fin active region and a second fin active region that are spaced apart from each other by a first distance,a third fin active region and a fourth fin active region that are spaced apart from each other by a second distance that is smaller than the first distance, andan edge fin active region; forming a sacrificial gate layer on the semiconductor substrate having the isolation region; forming a plurality of hard mask lines on the sacrificial gate layer, wherein the plurality of hard mask lines comprise a first hard mask line configured to cross the first and second fin active regions,a second hard mask line configured to cross the third and fourth fin active regions, andan edge hard mask line configured to cross the edge fin active region; forming a gate cut mask comprising a plurality of gate cut openings on the semiconductor substrate having the hard mask lines, wherein the plurality of gate cut openings comprise a first gate cut opening, a second gate cut opening, and an edge gate cut opening, wherein the first and second gate cut openings and the edge gate cut opening have line shapes that are parallel to each other,the first and second gate cut openings are spaced apart from each other and expose the first hard mask line on the sacrificial gate layer between the first and second fin active regions,the edge gate cut opening does not overlap the edge fin active region and exposes an end portion of the edge hard mask line,each of the first and second gate cut openings has a first width that are equal to each other, andthe edge gate cut opening has a second width that is greater than the first width but smaller than twice a size of the first width; etching the hard mask lines using the gate cut mask as an etch mask to form hard mask patterns; and removing the gate cut mask.
地址 Ansan-si KR