| 主权项 |
1. A method for fabricating a quasi SOI source-drain multi-gate device, comprising in sequence the following steps of:
(1) forming Fin strip-shaped active region on a first semiconductor material as a substrate by performing photolithography and etching; (2) forming a STI isolation layer by performing STI, wherein a backfill material for STI is insulating dielectric, the forming of the STI isolation layer is achieved by performing chemical vapor deposition (CVD) technology, chemical mechanical polishing technology and etching, and the Fin strip on the substrate has a height H1; (3) depositing sequentially a gate dielectric layer and a gate material layer on the substrate, and forming a gate stack structure by performing photolithography and etching using a gate-first process or a gate-last process, wherein the gate stack structure formed by the gate-first process is a true gate, the gate stack structure formed by the gate-last process is a dummy gate; (4) forming a doped structure of a source-drain extension region by implantation technology, and forming a first layer of sidewall with width L1 on both sides of the gate stack structure; (5) forming a U-shape recessed source-drain structures, a Σ-shape recessed source-drain structure or a S-shape recessed source-drain structure; (6) depositing a quasi SOI source-drain isolation layer by performing CVD, planarizing the quasi SOI source-drain isolation layer by performing CMP, which stops on the gate material layer, then performing etching back or isotropic wet etching on the quasi SOI source-drain isolation layer to form the quasi SOI source-drain isolation layer with thickness H5 on the recessed source-drain structure, wherein a material for the quasi SOI source-drain isolation layer is different from a material for a first layer of sidewall; (7) in-situ doping an epitaxial second semiconductor material to form the source and drain, and performing annealing to activate the source and drain; (8) if the gate-first process is used in the step (3), directly proceeding to step (9); if the gate-last process is used in the step (3), removing the gate stack structure as a dummy gate sacrificial layer and performing a deposition of a high k metal gate again, specifically comprising steps of: firstly, removing the dummy gate sacrificial layer by performing the isotropic wet etching, secondly forming a gate dielectric layer with high dielectric constant again by performing atomic layer deposition, then forming a gate material layer again by performing atomic layer deposition or physical vapor deposition, and finally planarizing the gate material layer by performing CMP; (9) forming a contact and a metal interconnection. |
