Interconnected arithmetic logic units

摘要

An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

主权项

1. An arithmetic logic stage circuit of a graphics processor unit pipeline, the circuit comprising:
a plurality of arithmetic logic units (ALUs) coupled in parallel to one another; and programmable interconnecting circuitry coupled between the ALUs and programmable according to programming code, wherein the interconnecting circuitry is operable to allow the plurality of ALUs to implement, on a single pass through the ALUs, a multiply-add operation according to a first programming code and a multidimensional dot product computation according to a second programming code, wherein the interconnecting circuitry comprises multiplexers coupling the parallel ALUs, the multiplexers comprising a multiplexer that routes data from one of the ALUs to another one of the ALUs, the multiplexers also comprising a multiplexer that receives data at one of the ALUs from another one of the ALUs.