LOW POWER BUFFER WITH GAIN BOOST

摘要

The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

主权项

1. A communication system comprising:
a clock source for providing a clock signal; an ADC module comprising a buffer circuit, wherein the buffer circuit comprises:
a first connection node, a first supply node;a first transistor coupled to the a first supply node and the first connection node, the first transistor being configured to process a first input signal;a second transistor coupled to the first connection node, the second transistor being configured to process a second input signal, second input signal being a complement of the first input signal; anda first bias circuit coupled to the second transistor, wherein the first transistor, the second transistor and the first bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a first target gain of one, the gain being defined by an output amplitude of a first output signal at the first connection node divided by an input amplitude of the first input signal.