| 摘要 |
PURPOSE:To obtain a device for measuring only a bit error rate or both the bit error rate and modulation accuracy simultaneously by providing a measurement section having the capacity of a memory capable of fetching data of N-slots at once to the device. CONSTITUTION:An AD buffer memory of a sampling section is provided with a measurement section 20 having a capacity of a memory capable of receiving data of N-slots at once and with a BER analysis section 30 receiving a demodulation signal from the measurement section 20 to analyze a bit error rate. Thus, PRBS data with consecutive N-slots or over are demodulated. That is, a synchronization parameter in one slot only of consecutive N-slot data is detected by an initial synchronization section to eliminate the need for a processing time to detect a synchronization parameter of another slots thereby realizing a high processing speed. Furthermore, a means to divided a sampling clock of the sampling section of the BFR analysis section 30 to 1/m so as to reduce the sampling resolutiion and conducting measurement is added to reduce succeeding processing time thereby attaining a high processing speed. |
