| 摘要 |
PURPOSE:To reduce the hardware amount of an arithmetic unit for executing the addition, subtraction, multiplication and division of floating point numbers. CONSTITUTION:In the case of floating point addition and subtraction, two mantissas for which digits are matched by a swapper 15 and a right shifter 16 are supplied through first and second mantissa selectors 17 and 18 and two pieces of one-bit right shifters 19 and 20 to an adder-subtractor 21 and added and subtracted in the adder-subtractor 21 and the result is rounded. In the case of floating point multiplication and divison, an intermediate sum S and a carry C outputted from a multiplier 24 are supplied through the first and second mantissa selectors 17 and 18 and two pieces of the one-bit right shifters 19 and 20 to the adder-subtractor 21 and added in the adder-subtractor 21 and the result is rounded. The rounded result of the adder-subtractor 21 is passed through a priority encoder 22 and a left shifter 23 and outputted as the normalized mantissa. Exponents are processed by exponent computing units 11, 13 and 14 and an exponent selector 12. |
