发明名称 Semiconductor memory device
摘要 This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
申请公布号 US9368555(B2) 申请公布日期 2016.06.14
申请号 US201414178636 申请日期 2014.02.12
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Okawa Takamasa;Tsukamoto Takayuki;Minemura Yoichi;Kanno Hiroshi;Yoshida Atsushi;Tabata Hideyuki
分类号 H01L27/24;G11C13/00;H01L45/00 主分类号 H01L27/24
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A semiconductor memory device, comprising: a memory cell array including: a first conductive line, the first conductive line extending in a first direction; second conductive lines, the second conductive lines extending in a second direction intersecting the first direction; a variable resistance element, the variable resistance element being disposed at an intersection of the first conductive line and the second conductive lines and disposed between the first conductive line and the second conductive lines; a third conductive line, the third conductive line extending in a third direction intersecting the first direction; and a select transistor, the select transistor including a gate electrode, a gate insulating film, and a semiconductor layer, the semiconductor layer disposed between an end of the first conductive line at a side in the first direction and the third conductive line; and a non-linear resistance layer disposed between the end of the first conductive line at the side in the first direction and the semiconductor layer, the non-linear resistance layer being configured from a non-linear material.
地址 Minato-ku JP