发明名称 Digital circuit having correcting circuit and electronic apparatus thereof
摘要 Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.
申请公布号 US9368526(B2) 申请公布日期 2016.06.14
申请号 US201414250663 申请日期 2014.04.11
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kimura Hajime
分类号 H01H47/00;H02B1/24;H01L27/12;H03K19/017;G02F1/1368;H01L27/06 主分类号 H01H47/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a capacitor, wherein a gate of the first transistor is electrically connected to one of a pair of terminals of the capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to an output terminal, wherein the one of the pair of terminals of the capacitor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the pair of terminals of the capacitor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the pair of terminals of the capacitor is electrically connected to one of a source and a drain of the fifth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the fifth transistor is electrically connected to a third wiring, wherein the first wiring is configured to be supplied with a power supply voltage, wherein the second wiring is configured to be supplied with a signal, and wherein the third wiring is configured to be supplied with a constant voltage.
地址 Atsugi-shi, Kanagawa-ken JP