发明名称 Partial erase verify
摘要 A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.
申请公布号 US7468926(B2) 申请公布日期 2008.12.23
申请号 US20060335321 申请日期 2006.01.19
申请人 SAIFUN SEMICONDUCTORS LTD. 发明人 SHAPPIR ASSAF;EISEN SHAI
分类号 G11C7/00 主分类号 G11C7/00
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