| 发明名称 | Memory systems | ||
| 摘要 | Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries. | ||
| 申请公布号 | US9489301(B2) | 申请公布日期 | 2016.11.08 |
| 申请号 | US201414246357 | 申请日期 | 2014.04.07 |
| 申请人 | Micron Technology, Inc. | 发明人 | Gorobets Sergey Anatolievich;Bennett Alan David;Sinclair Alan Welsh |
| 分类号 | G06F12/02;G06F3/06;G11C16/10;G11C16/34 | 主分类号 | G06F12/02 |
| 代理机构 | Dicke, Billig & Czaja, PLLC | 代理人 | Dicke, Billig & Czaja, PLLC |
| 主权项 | 1. A memory system comprising: a volatile memory; a non-volatile memory arranged in blocks; and a controller coupled to the volatile memory and to the non-volatile memory, the controller configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory; wherein the controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory when the list is updated to contain a predetermined number of list entries; and wherein the predetermined number of list entries is greater than one. | ||
| 地址 | Boise ID US | ||