| 发明名称 |
Large-Scale Complementary Macroelectronics Using Hybrid Integration of Carbon Nanotubes and Oxide Thin-Film Transistors |
| 摘要 |
A method of fabricating a logic element, the method includes forming a p-type nanomaterial thin film transistor on a substrate, forming a n-type metal oxide thin film transistor on the substrate, and connecting the p-type nanomaterial thin film transistor to the n-type metal oxide thin film transistor to form the logic element. The logic element is a hybrid complementary logic element. |
| 申请公布号 |
US2016351629(A1) |
申请公布日期 |
2016.12.01 |
| 申请号 |
US201615167943 |
申请日期 |
2016.05.27 |
| 申请人 |
University of Southern California |
发明人 |
Zhou Chongwu;Chen Haitian;Cao Yu;Zhang Jialu;Vuttipittayamongkol Pattaramon;Wu Fanqi;Cao Xuan |
| 分类号 |
H01L27/28;H01L29/786;H01L29/24;H01L51/00;H01L51/05 |
主分类号 |
H01L27/28 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of fabricating a logic element, the method comprising:
forming a p-type nanomaterial thin film transistor on a substrate; forming a n-type metal oxide thin film transistor on the substrate; and connecting the p-type nanomaterial thin film transistor to the n-type metal oxide thin film transistor to form the logic element, wherein the logic element is a hybrid complementary logic element. |
| 地址 |
Los Angeles CA US |
