COMPACT ReRAM BASED PFGA

摘要

A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.

主权项

1. A method for fabricating a push-pull resistive random access memory cell circuit comprising:
the output node and the second bit line; forming source and drain regions for first and second programming transistors in a semiconductor substrate, the drain region for the second programming transistor connected to the source of the first programming transistor, the source and drain regions for first and second programming transistors formed such that the first and second programming transistors have an equal pitch and an equal channel length; forming gate dielectric regions over the source and drain regions for first and second programming transistors, the gate dielectric regions having equal thicknesses chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit; forming gate regions for the first and second programming transistors over the gate dielectric regions; forming a first dielectric region over the gates of the first and second programming transistors; forming in the first dielectric region a drain contact to the drain of the first programming transistor, a source contact to the source of the second programming transistor, and gate contacts to the gates of the first and second programming transistors; forming an output node, a word line source, and a word line for the memory cell circuit in a first metal interconnect layer, the output node connected to the drain contact, the word line source connected to the source contact, and the word line connected to the gate contacts of the first and second programming transistors; forming first and second resistive random access memory devices each having first and second terminals, the first terminal of each of the first and second resistive random access memory devices connected to the output node; forming a second dielectric region over the second terminals of the first and second resistive random access memory devices; forming in the second dielectric region a first bit line contact to the second terminal of the first resistive random access memory device and a second bit line contact to the second terminal of the second resistive random access memory device; and forming first and second bit lines in a second metal interconnect layer, the first bit line connected to the first bit line contact and the second bit line connected to the second bit line contact.