发明名称 |
RECESSED HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR FOR RRAM CELL |
摘要 |
A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor. |
申请公布号 |
US2016351625(A1) |
申请公布日期 |
2016.12.01 |
申请号 |
US201514726071 |
申请日期 |
2015.05.29 |
申请人 |
Crossbar, Inc. |
发明人 |
Gee Harry Yue;Kumar Tanmay;Vasquez, JR. Natividad;Maxwell Steven Patrick;Narayanan Sundar |
分类号 |
H01L27/24;H01L29/78;H01L29/423;H01L29/66;H01L21/265 |
主分类号 |
H01L27/24 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method for fabricating a MOS transistor for a two-terminal memory device, comprising:
forming a gate recess into a surface of a semiconductor substrate; depositing an electrically insulating dielectric layer at least over a recess surface of the semiconductor substrate exposed by the gate recess; forming a recess gate over and at least in part within the gate recess, extending below the top surface of the semiconductor substrate; forming a source and a drain in the semiconductor substrate on opposing sides of the recessed gate; and forming the two-terminal memory device over the semiconductor substrate and in electrical series with the source or the drain. |
地址 |
Santa Clara CA US |