Fabrication Methodology For Optoelectronic Integrated Circuits

摘要

A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) n-type modulation doped quantum well structure (MDQWS) structure with n-type charge sheet, ii) p-type MDQWS, iii) undoped spacer layer formed on the n-type charge sheet, iv) p-type layer(s) formed on the undoped spacer layer, v) p-type etch stop layer formed on the p-type layer(s) of iv), and vi) p-type layers (including p-type ohmic contact layer(s)) formed on the p-type etch stop layer. An etch operation removes the p-type layers of vi) for a gate region of an n-channel HFET with an etchant that automatically stops at the p-type etch stop layer. Another etch operation removes the p-type etch stop layer to form a mesa at the p-type layer(s) of iv) which defines an interface to the gate region of the n-channel HFET, and a gate electrode is formed on such mesa.

主权项

1. A method of forming an integrated circuit comprising:
depositing or providing a plurality of layers supported on a substrate, wherein the plurality of layers includes i) an n-type modulation doped quantum well structure with an n-type charge sheet, ii) a p-type modulation doped quantum well structure with a p-type charge sheet offset vertically from the n-type modulation doped quantum well structure, iii) an undoped spacer layer formed on the n-type charge sheet, iv) at least one p-type layer of relatively high concentration of p-type doping formed on the undoped spacer layer, v) at least one p-type etch stop layer formed on the at least one p-type layer of iv), and vi) a plurality of p-type layers formed on the at least one p-type etch stop layer, wherein the plurality of p-type layers includes at least one p-type ohmic contact layer; performing an etch operation (E1) that removes the plurality of p-type layers of vi) for a gate region of an n-channel HFET of the integrated circuit, wherein the E1 etch operation employs an etchant that automatically stops at the at least one p-type etch stop layer for the gate region of the n-channel HFET; performing an etch operation (E2) that removes remaining portions of the at least one p-type etch stop layer to form a mesa at the at least one p-type layer of iv) below the at least one p-type etch stop layer, wherein the mesa at the at least one p-type layer of iv) formed by the E2 etch operation defines an interface to the gate region of the n-channel HFET; and forming a gate electrode for the n-channel HFET on the mesa at the at least one p-type layer of iv) as formed by the E2 etch operation.