SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS

摘要

Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

主权项

1. A method of fabricating a portion of a nanowire field effect transistor (FET), the method comprising:
forming a sacrificial layer and a nanowire layer; removing a sidewall portion of the sacrificial layer; forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer; forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region; and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.