BUILT-IN SELF-TEST (BIST) CIRCUIT AND ASSOCIATED BIST METHOD FOR EMBEDDED MEMORIES

摘要

Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

主权项

1. An integrated circuit chip comprising:
a plurality of memories; and a built-in self-test circuit comprising a built-in self-test engine electrically connected to multiple memories of said plurality of memories, said built-in self-test engine comprising an address generator, said address generator determining a superset of address space values indicating a highest number of banks in any of said multiple memories, a highest number of word lines per bank in any of said multiple memories and a highest decode number for any of said multiple memories, and said address generator further generating test addresses for testing said multiple memories, said test addresses being generated such that all of said test addresses are within a composite address space defined by said superset.