PICTURE SIGNAL PROCESSOR

摘要

A PAL plus signal of the interlace system is supplied to a 133-line delay 22 as a delay element of 133 lines. An output of the delay element is supplied to a field memory 23 and a field memory 25. The field memory 23 is a first memory to delay by one field. An output of the field memory 23 is supplied to a field memory 24 as a second memory. The field memory 24 executes a shuffling process with respect to an A field and reads out the A field at a double speed so that the same A field continues four times. The field memory 25 as a third memory is controlled so as to start the reading operation with a predetermined time delay for the writing operation, executes a shuffling process with respect to a B field, and reads out the B field at a double speed so that the same B field continues four times. The image signals read out from the memories 24 and 25 are supplied to a vertical filter median processing unit 26 as scanning line interpolating means. <IMAGE>