LOGIC SIMULATION METHOD THAT PERFORMS TIMING VERIFICATION WHILE TAKING JITTER OF PLL BLOCK INTO ACCOUNT AND ITS LOGIC SIMULATOR

摘要

PROBLEM TO BE SOLVED: To provide a logic simulation method which performs timing verification while taking jitters of a PLL block into account and its logic simulator. SOLUTION: When the timing of a circuit having a PLL block is verified by an event-driven type logic simulation method, a jitter value characteristic of the PLL block included in a target circuit is described in a delay library and added to or subtracted from the result obtained by timing verification, thereby performing the timing verification while the jitter value is taken into consideration according to whether the setup and hold of the target circuit are satisfied.