Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit

摘要

A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

主权项

1. An integrated circuit, comprising:
an electrically conductive carrier; a chip mounted on a top side of the carrier; encapsulation material at least partially covering the chip and the carrier; at least one interconnect disposed within the encapsulation material electrically connecting the chip to the carrier; a layer stack disposed over the carrier on a bottom side of the carrier opposite the top side of the carrier, the layer stack comprising:
a plurality of discrete polymer layers, wherein at least one of the polymer layers is disposed over the carrier and disposed on at least a portion of a bottom side of the encapsulation material; andone or more discrete ceramic layers, wherein at least one of the ceramic layers is disposed between a pair of the plurality of the polymer layers;wherein a first layer and a last layer of the layer stack is each a polymer layer; wherein the first layer of the layer stack is connected to the last layer of the polymer stack so that the first layer and the second layer wrap around the layer stack; wherein the carrier comprises an extension so that the encapsulation material and the layer stack do not cover any surface of the carrier extension.