主权项 |
1. A semiconductor integrated circuit comprising:
an address decoder configured to decode address signals and provide a plurality of test mode control signals of first and second groups; and
a test mode control unit configured to generate a reset signal and test mode signals of the first and second groups in response to a test mode activation signal and the plurality of the test mode control signals,wherein the test mode control unit includes:a test mode reset signal generating unit configured to receive the plurality of test mode control signals and generate test mode signals of the second group and the reset signal at a test mode; anda test mode signal selection unit configured to receive the plurality of test mode control signals and the reset signal, and generate a plurality of test mode signals of the first group,wherein when the reset signal is activated, all the plurality of the test mode signals of the first group are inactivated, and the plurality of the test mode signals of the second group are activated with maintaining the test mode, andwhen the reset signal is inactivated, the plurality of the test mode signals of the first group are activated. |