发明名称 Semiconductor integrated circuit capable of controlling test modes without stopping test
摘要 A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.
申请公布号 US9368237(B2) 申请公布日期 2016.06.14
申请号 US200912483372 申请日期 2009.06.12
申请人 HYNIX SEMICONDUCTOR INC. 发明人 An Sun Mo;Chu Shin Ho
分类号 G11C29/46 主分类号 G11C29/46
代理机构 Ladas & Parry LLP 代理人 Ladas & Parry LLP
主权项 1. A semiconductor integrated circuit comprising: an address decoder configured to decode address signals and provide a plurality of test mode control signals of first and second groups; and a test mode control unit configured to generate a reset signal and test mode signals of the first and second groups in response to a test mode activation signal and the plurality of the test mode control signals,wherein the test mode control unit includes:a test mode reset signal generating unit configured to receive the plurality of test mode control signals and generate test mode signals of the second group and the reset signal at a test mode; anda test mode signal selection unit configured to receive the plurality of test mode control signals and the reset signal, and generate a plurality of test mode signals of the first group,wherein when the reset signal is activated, all the plurality of the test mode signals of the first group are inactivated, and the plurality of the test mode signals of the second group are activated with maintaining the test mode, andwhen the reset signal is inactivated, the plurality of the test mode signals of the first group are activated.
地址 Gyeonggi-do KR