| 摘要 |
A jitter control circuit (100) within a chip (102) includes an adaptive PDN (1 10), a current generator (120) and a jitter generator (160). The adaptive PDN (110) is capable of being controlled/modulated to provide difference impedances. The current generator (120) is coupled to the adaptive PDN (110), and is arranged for receiving a supply voltage provided by the adaptive PDN (110) and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN (1 10), and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN (110). |
