Bootstrapped high-speed output buffer

摘要

An output buffer circuit comprises an input terminal for receiving an input signal, an output circuit coupled to a first node for outputting an output signal in response to a potential level appeared on the first node and a bootstrap circuit coupled between the first node and the input terminal. The bootstrap circuit comprises a delay circuit for delaying the input signal to provide a delayed input signal, a first transistor for receiving a signal inverted from the input signal, a second transistor coupled for receiving the delayed input signal and controlling a the first transistor, a third transistor connected in parallel to the second transistor, a fourth transistor coupled a gate of the third transistor for receiving the input signal and a charge circuit coupled between the delay circuit and the first node for supplying an electric charge to the first node. The charge circuit is activated in response to the potential level appeared on the first node and the delayed input signal.