发明名称 |
Semiconductor integrated circuit device |
摘要 |
A selection circuit is provided for first and second latch circuits which operate in response to first and second operation timing signals, respectively. By the selection circuit, a first operation of transmitting a signal corresponding to a first output signal of the first latch circuit to a third output terminal, and a second operation of transmitting a second output signal in place of the first output signal to the third output terminal when the first output is different from the second output signal of the second latch circuit are performed. The second operation timing signal is generated behind the first operation timing signal, and the operation period of the second latch circuit is shortened as necessary in the first operation.
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申请公布号 |
US2001038569(A1) |
申请公布日期 |
2001.11.08 |
申请号 |
US20010842865 |
申请日期 |
2001.04.27 |
申请人 |
FUJISAWA HIROKI;HORIGUCHI MASASHI |
发明人 |
FUJISAWA HIROKI;HORIGUCHI MASASHI |
分类号 |
G11C11/409;G11C7/10;G11C7/22;G11C8/18;G11C11/401;G11C29/34;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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