发明名称 |
Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug |
摘要 |
In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
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申请公布号 |
US6396149(B1) |
申请公布日期 |
2002.05.28 |
申请号 |
US20000593284 |
申请日期 |
2000.06.13 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
YUAN XUEJUN;JIN XIAOWEI;PYAPALI RAMBABU;HEALD RAYMOND A.;KAKU JAMES M.;DUNN HELEN;TAYLOR THELMA C.;LAI PETER F.;OSTRER AHARON |
分类号 |
H01L21/66;H01L23/525;(IPC1-7):H01L27/10;H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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