Semiconductor Device

摘要

To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

主权项

1. A semiconductor device, comprising:
a wiring substrate; an interposer mounted over a first surface of the wiring substrate; a first semiconductor chip mounted over the interposer; and a second semiconductor chip which is mounted over the interposer side by side with the first semiconductor chip and controls the first semiconductor chip, wherein the interposer has a plurality of wiring layers including a first wiring layer, and a second wiring layer laminated over the first wiring layer, wherein the first semiconductor chip and the second semiconductor chip are electrically coupled through a plurality of wirings formed in the wiring layers of the interposer, wherein the wirings includes:
a first reference potential wiring formed in the first wiring layer and extending from one of the first semiconductor chip and the second semiconductor chip to the other thereof,a second reference potential wiring formed in the first wiring layer and extending along the first reference potential wiring,a first signal wiring formed in the first wiring layer and extending along the first reference potential wiring and the second reference potential wiring between the first reference potential wiring and the second reference potential wiring,a third reference potential wiring formed in the second wiring layer and extending from one of the first semiconductor chip and the second semiconductor chip to the other thereof,a fourth reference potential wiring formed in the second wiring layer and extending along the third reference potential wiring, anda second signal wiring formed in the second wiring layer and electrically isolated from the first signal wiring, and extending along the third reference potential wiring and the fourth reference potential wiring between the third reference potential wiring and the fourth reference potential wiring, wherein the first reference potential wiring is coupled to the third reference potential wiring through a first coupling portion and coupled to the fourth reference potential wiring through a second coupling portion, and has a first crossing portion crossing the second signal wiring between the first coupling portion and the second coupling portion in plan view, and wherein the second reference potential wiring is coupled to the third reference potential wiring through a third coupling portion and coupled to the fourth reference potential wiring through a fourth coupling portion, and has a second crossing portion crossing the first signal wiring between the third coupling portion and the fourth coupling portion in plan view.