Delta sigma modulator apparatus and method to mitigate DAC error induced offset and even order harmonic distortion

摘要

Delta sigma modulators, apparatus and methods mitigate DAC error induced offset and even order harmonic distortion in a delta sigma modulator by chopping a digital output stream of a forward circuit path using a digital modulator or digital chopper circuit in a feedback circuit to create a DAC digital input signal responsive to a chopper clock signal having a clock rate lower than a DSM quantizer clock signal, and chopping a differential DAC output signal using an analog chopper circuit responsive to the chopper clock signal to provide a differential feedback signal to a forward circuit path of the DSM to mitigate DAC error induced offset and even order harmonic distortion in the digital output stream.

主权项

1. A delta sigma modulator (DSM), comprising:
a summer circuit operative to sum a differential analog input signal and a differential feedback signal, and to provide a differential summer output signal; a first integrator in a forward circuit, the first integrator including: first and second integrator inputs to receive the differential summer output signal, and first and second integrator outputs to provide a first differential integrator output signal; a quantizer connected after the first integrator in the forward circuit path, the quantizer including: first and second quantizer inputs to receive a differential quantizer input signal, and a quantizer output to provide a digital output stream corresponding to the analog input signal by quantifying the differential quantizer input signal responsive to a first clock signal; a first digital to analog converter (DAC) in a feedback circuit forming a closed loop around the forward circuit, the first DAC including: a DAC input to receive a DAC digital input signal, and first and second DAC outputs to provide a differential DAC output signal corresponding to the DAC digital input signal; an analog chopper circuit in the feedback circuit between with the first DAC and the summer circuit, the analog chopper circuit operative to provide the differential feedback signal to the summer circuit according to the differential DAC output signal with alternating polarity responsive to a second clock signal; and a digital chopper circuit coupled in the feedback circuit between the quantizer output and the DAC input to selectively invert the digital output stream to provide the DAC digital input signal responsive to the second clock signal.