| 摘要 |
<p>PURPOSE: To reduce the difference between the internal time in the processor and reference time. CONSTITUTION: A receiving circuit 1 when receiving reference time data through a communication path 100 outputs a reception information signal 111. A processing part 2 when inputting the reception information signal 111 reads a counted value out of a holding circuit 3 and decides the difference between the reference time data and internal time data. The processing part 2 sets a frequency division ratio in a frequency division ratio setting circuit 4 according to the decision result. The holding circuit 3 when inputting the reception information signal 11 holds the current counted value of a frequency dividing circuit 6. The frequency dividing circuit 6 divides the frequency of the clock signal from an oscillator 5 by the frequency division ratio set in the frequency division setting circuit 4 and outputs a count-up signal 112 to the timer part 7 when the counted value reaches the value set in the frequency division ratio setting circuit 4. The timer part 7 performs counting operation each time the count-up signal 112 is inputted to clock the internal time.</p> |
