DESIGN DEVICE FOR CLOCK OF SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN AND CLOCK FEED CIRCUIT NETWORK THEREOF

摘要

PROBLEM TO BE SOLVED: To reduce a difference in the delays of the clocks of a semiconductor integrated circuit, by a method wherein a load capacitance adjusting means is constituted into a structure, wherein a dummy buffer circuit, a dummy clock input circuit and a dummy wiring are connected with each circuit on the basis of a difference between the load capacitances of the circuits, which is obtained by calculating the load capacitances, to adjust the load capacitances of the circuits roughly equal to each other. SOLUTION: Differences between the terminal capacitances 201 to 204, 205 to 208, 209 and 210 and 211 to 213 of clock input terminals 101 to 104, 105 to 108, 109 and 110 and 111 to 113, which are respectively connected with buffer elements 202, 203, 306 and 307, are calculated. The total terminal capacitances of the element 302, the total terminal capacities of the element 303, the total terminal capacitances of the element 306 and the total terminal capacitances of the element 307 are respectively denoted as the reference numerals 4, 5, 2 and 3. As the largest total terminal capaictances among the total terminal capacitances are the reference numeral 5 of the element 303, the wiring capacitance of a wiring of the component 1 of a difference between the total terminal capacitances of the elements 303 and 302, the wiring capacitance of a wiring of the component 3 of a difference between the total terminal capacitances of the elements 303 and 306, and the wiring capacitance of a wiring of the component 2 of a difference between the total terminal capacitances of the elements 303 and 307, are respectively added to each of the other buffer elements 302, 306 and 307 to equally adjust the load capacitances of the elements 302, 303, 306 and 307 to each other.