发明名称
摘要 <p>PURPOSE:To securely insert stuff bits with simple configuration by executing a processing while raising a stuff flag at a stuff bit inserting position in advance. CONSTITUTION:When converting data, to which a variable length code processing is executed, to parallel variable length code data Dr, the stuff bits Dr are raised at the stuff bit inserting position in advance and afterwards transmitted to a stuff bit adding circuit 34 together with encoded data DVLC. Therefore, the stuff bit inserting position and the amount of data in a data buffer circuit 33A can be detected. Thus, stuff bits DSTU can securely be inserted with simple configuration.</p>
申请公布号 JP2864632(B2) 申请公布日期 1999.03.03
申请号 JP19900055524 申请日期 1990.03.07
申请人 SONII KK 发明人 NAMIKI KAZUHIKO
分类号 H04N19/102;H04N1/41;H04N7/24;H04N19/00;H04N19/107;H04N19/117;H04N19/126;H04N19/134;H04N19/146;H04N19/152;H04N19/176;H04N19/186;H04N19/196;H04N19/423;H04N19/46;H04N19/463;H04N19/503;H04N19/51;H04N19/517;H04N19/587;H04N19/59;H04N19/61;H04N19/625;H04N19/65;H04N19/70;H04N19/82;H04N19/85;H04N19/86;H04N19/89;H04N19/91;(IPC1-7):H04N7/24 主分类号 H04N19/102
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