发明名称 Back end of line integration scheme
摘要 A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal layers, each of the second metal layers is over one of the second ILDs. The first ILD is not cured. It has a k value of between about 2.5 and about 3.0, a pore size of smaller than about 10 Å, and a hardness of greater than about 1.5 Gpa. The second ILDs are cured therefore having lower k values of smaller than about 2.5, pore sizes of greater than about 10 Å, and hardness of smaller than about 1.5 Gpa. The semiconductor structure has reduced plasma charge damage from plasma curing.
申请公布号 US2006125102(A1) 申请公布日期 2006.06.15
申请号 US20040012406 申请日期 2004.12.15
申请人 WU ZHEN-CHENG;CHEN YING-TSUNG;CHEN PI-TSUNG;LU YUNG-CHENG 发明人 WU ZHEN-CHENG;CHEN YING-TSUNG;CHEN PI-TSUNG;LU YUNG-CHENG
分类号 H01L23/52;H01L21/4763 主分类号 H01L23/52
代理机构 代理人
主权项
地址