发明名称 SERIAL INTERFACE AND PROCESS FOR REAL-TIME BIT ERROR RATE TESTING
摘要 <p>A serial interface (IFl, IF2) is intended for being connected to data communication equipments in a communication network and is adapted to transmit and/or receive streams of serial data blocks. This serial interface (IFl, IF2) comprises i) a detection means (DM) for reading at least partly each received stream data block to detect a parity data included in each data block, ii) a control means (CM) for checking the parity of the data contained in each received stream data block (excepted the associated parity data) in order to deliver a computed parity data, iii) a first storing means (Ml) for storing a value representative of the number of parity failures, and iv) a processing means (PM) for comparing each detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and, in case of comparison data representative of a parity failure, to increment by one the value stored into the first storing means (Ml) and then to carry out a new parity comparison relative to the next stream data block.</p>
申请公布号 WO2006134539(A9) 申请公布日期 2007.04.19
申请号 WO2006IB51858 申请日期 2006.06.12
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;DERCKX, HENRICUS PETRONELLA MARIA;RUIGT, DOLF 发明人 DERCKX, HENRICUS PETRONELLA MARIA;RUIGT, DOLF
分类号 H04L1/24;H04L1/20 主分类号 H04L1/24
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