| 摘要 |
PROBLEM TO BE SOLVED: To easily verify an asynchronous circuit in a short time after generation of a netlist. SOLUTION: Erroneous operation can be easily detected, when a logic synthesis means 2 generates the netlist 11 by logic synthesis, an extraction means 3 extracts delay information and an asynchronous circuit part 13 from the generated netlist, a delay information processing means 4 processes the delay information to prolong an erroneous operation occurrence term of the asynchronous circuit part 13, and a simulation means 5 verifies the asynchronous circuit by using the processed delay information. In this way, verification of the asynchronous circuit can be carried out in a short time. COPYRIGHT: (C)2008,JPO&INPIT
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