H-bridge gate control circuit

摘要

A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal. The control circuit includes: two high side switches configured to be connected with the voltage source respectively through the power terminal; two low side switches configured to be connected with the ground reference respectively through the ground terminal; a first inverter connecting the two high side switches; a second inverter connecting the two low side switches; and a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively.

主权项

1. A gate control circuit for controlling gates of at least a half side of an H-bridge circuit, the gate control circuit comprising:
an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal, the control circuit comprising:
two high side switches configured to be connected with the voltage source respectively through the power terminal;two low side switches configured to be connected with the ground reference respectively through the ground terminal;a first inverter connecting the two high side switches;a second inverter connecting the two low side switches;a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively;a first capacitor connected between the power terminal and an input of the first inverter; anda second capacitor connected between the ground terminal and an input of the second inverter; wherein: one of the high side switches and one of the low side switches are respectively connected with the input terminal and configured to be controlled by the PWM signal; and the high side switches are respectively open when high inputs are fed to gates thereof and closed when low inputs are fed to gates thereof, while the low side switches are respectively open when low inputs are fed to gates thereof and closed when high inputs are fed to gates thereof.