| 发明名称 |
Mechanism To Avoid Hot-L1/Cold-L2 Events In An Inclusive L2 Cache Using L1 Presence Bits For Victim Selection Bias |
| 摘要 |
A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status. |
| 申请公布号 |
US2016283380(A1) |
申请公布日期 |
2016.09.29 |
| 申请号 |
US201514671411 |
申请日期 |
2015.03.27 |
| 申请人 |
Intel Corporation |
发明人 |
Vinod Krishna N.;Sodani Avinash;Aurangabadwala Zainulabedin |
| 分类号 |
G06F12/08;G06F12/12 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
a processing core; an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item; an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry; an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry; and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status. |
| 地址 |
Santa Clara CA US |
