Low-power, high-speed successive approximation register analog-to-digital converter and conversion method using the same

摘要

Provided is a low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The low-power, high-speed SAR ADC includes a bootstrapping unit configured to receive inputs of first and second analog signals, a double-bit output SAR analog-to-digital conversion unit configured to output a two-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit, and a single-bit output SAR analog-to-digital conversion unit configured to output a one-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit.

主权项

1. A low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC) comprising:
a bootstrapping unit configured to receive inputs of first and second analog signals; a double-bit output SAR analog-to-digital conversion unit configured to output a two-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit; and a single-bit output SAR analog-to-digital conversion unit configured to output a one-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit; wherein the bootstrapping unit includes first to third bootstrapping switch pairs, wherein the first and second bootstrapping switch pairs apply the first and second analog signals to the double-bit output SAR analog-to-digital conversion unit, and wherein the third bootstrapping switch pair applies the first and second analog signals to the single-bit output SAR analog-to-digital conversion unit.