发明名称 Method of semiconductor integrated circuit fabrication
摘要 A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench.
申请公布号 US9478430(B2) 申请公布日期 2016.10.25
申请号 US201414532462 申请日期 2014.11.04
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Yao Hsin-Chieh;Tsai Cheng-Hsiung;Lee Chung-Ju;Bao Tien-I
分类号 H01L21/02;H01L23/48;H01L21/308;H01L21/768 主分类号 H01L21/02
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising: depositing a first dielectric layer on a substrate; forming a patterned photoresist layer on the first dielectric layer to have opaque regions and openings; trimming the opaque regions; etching the first dielectric layer through the patterned photoresist layer to form a dielectric feature; forming sacrificing-energy-decomposable-layer (SEDL) spacers along sidewalls of the dielectric feature; forming dielectric spacers along sidewalls of the SEDL spacers; and decomposing the SEDL spacers to form trenches over the substrate.
地址 Hsin-Chu TW