Methods and apparatuses including command latency control circuit

摘要

Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.

主权项

1. An apparatus comprising:
a counter circuit configured to receive a first clock signal and produce a plurality of first signals responsive to the first clock signal; a delay circuit coupled to the counter circuit and configured to provide a plurality of second signals by delaying the plurality of first signals; and a latch circuit configured including a plurality of holding circuits, wherein an input of each of the plurality of holding circuits is coupled to a first circuit node and an output of each of the plurality of holding circuits is coupled to a second circuit node, wherein individual ones of the plurality of holding circuits are configured to latch an input signal on the first circuit node responsive to an assertion of a respective one of a plurality of input enable signals, wherein the individual ones of the plurality of holding circuits are further configured to output an output signal to the second circuit node responsive to an assertion of a respective one of a plurality of output enable signals, wherein individual ones of the plurality of input enable signals are asserted based on at least one of the plurality of first signals and individual ones of the plurality of output enable signals are asserted based on at least one of the plurality of second signals.