发明名称 SEMICONDUCTOR STRUCTURE AND PROCEDURE FOR MINIMISING NON-IDEALITIES
摘要 The invention relates to a semiconductor structure and a method for minimising non-idealities in a semiconductor structure, in which a drain, a source, a floating gate (102) and at least one input (108) capacitively connected to the floating gate (102) are disposed on a substrate (105) so as to form a nu -MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate (102) and at least partially superimposed on the gate (102) is formed in the semiconductor structure and the conductive layer is connected to a constant potential.
申请公布号 WO9967827(A2) 申请公布日期 1999.12.29
申请号 WO1999FI00494 申请日期 1999.06.08
申请人 VALTION TEKNILLINEN TUTKIMUSKESKUS VTT;RANTALA, ARTO 发明人 RANTALA, ARTO
分类号 G11C27/00;H01L27/115;H01L29/788 主分类号 G11C27/00
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