发明名称 |
Method of planarization using dummy leads |
摘要 |
An Integrated Circuit Design which adds, to the standard conducting lines of the bulk metal layer, a pattern of a support structure which supports subsequent deposition in such a way that it eliminates previously experienced concavity or dishing of the subsequent deposition within areas which have a low density or absence of conducting lines. The dummy pattern enhances the deposition of filler material between conducting lines of the Integrated Circuit such that planarization of the bulk metal results in a smoother surface of the areas of the signal lines of the integrated circuit and within large open areas. Concurrently the present invention provides a means of successfully collecting data that are needed for Damascene processing.
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申请公布号 |
US6156660(A) |
申请公布日期 |
2000.12.05 |
申请号 |
US19990244883 |
申请日期 |
1999.02.05 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
LIU, CHI-WEN;TSAI, CHIA-SHIUNG;LIU, JING-MENG;SHIH, TSU |
分类号 |
H01L21/768;(IPC1-7):H01L21/44;H01L21/461 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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