BUS BRIDGE CIRCUIT AND DATA PROCESSING SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a bus bridge circuit and data processing system do not cause a CPU to deteriorate in the performance of memory access while evading a bus deadlock. SOLUTION: The bus bridge circuit 20 which connects a processor bus 2 where a CPU 10 is connected and an external bus 3 where an external device 70 is connected is provided with a memory connecting line connected to an external memory, a processor bus connecting line connected to the processor bus, an external bus connecting line connected to the external bus, and a 1st switching means 26 which switches the connection of the memory connecting line to one of the processor bus connecting side and external bus connecting line side; when memory access from the processor bus side is gained, the 1st switching means 26 connects the processor bus connecting line and memory connecting line directly to each other.