摘要 |
A semiconductor memory device, including a plurality of cell arrays, each cell array configured to receive and output data through first data IO lines and including at least one block having memory cells corresponding to a plurality of column selecting lines, a redundancy cell array configured to receive and output data through redundancy data IO lines and including redundancy memory cells corresponding to n redundancy column selecting lines, 2<SUP>m </SUP>switching circuits configured to operate in correspondence with 2<SUP>m </SUP>line selecting signals, the switching circuits configured to transmit data from second data IO lines to first data IO lines or to redundancy data IO lines, n switch selecting portions each having m fuses, the switch selecting generating portions configured to program the second fuses to generate 2<SUP>m </SUP>switch control signals, and 2<SUP>m </SUP>selecting signal generating portions configured to output line selecting signals.
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