| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock and data recovery (CRD) system and method that recovers timing information and data from a serial data stream. <P>SOLUTION: A CDR system (100) has a sampling circuit (105) generating a clock/data signal that is in a recovery state, and an interleaving feedback network (110). This network has a logic circuit (115) generating a control signal based on a recovery signal, a first multiplexer (120) selecting from four phases of a global clock signal based on the control signal, a first delay locked loop (130) including a first set of delay cells coupled to a second multiplexer that generates a delay signal based on the selected global clock signal, and a second delay locked loop (135) including a second set of delay cells that generates a set of phase-shifted feedback signals. <P>COPYRIGHT: (C)2008,JPO&INPIT |
